Semiconductor wafers use increasingly expensive materials, fabrication equipment, and computing resources as successive technology nodes are brought into production. Therefore, wafer processes are carefully honed to ensure that these materials, equipment, and resources are not wasted. For example, irregularities in the surface of a wafer may result in less than optimal functioning of the electronic devices formed by the wafer or even non-functional electronic devices. As a result, the manufacture of modern nanometer-scale electronic devices requires the accurate measurement and control of substrate flatness and geometry. Indeed, tolerance to nanometer-scale deviations from perfect planarity and thickness uniformity is constantly tightening as the semiconductor industry shrinks minimum photolithography feature sizes and corresponding depth-of-focus (DOF) budgets.
Another issue of continuing concern in the semiconductor industry is the edge profile of the wafer, particularly a wafer constructed from a brittle substrate material such as crystalline silicon, quartz, or sapphire. The sharp corner at the edge of a wafer is typically macroscopically rounded to avoid edge chipping in the course of normal handling. In turn, this chipping may result in stress risers, thereby increasing the probability of substrate breakage, especially during high temperature processing.
To fabricate the maximum possible number of devices on a substrate, the edge profile would ideally have no effect on planarity up to a few tenths of a millimeter from the apex of the edge. However, in practice, substrate front-surface grinding and polishing operations are performed after macroscopic rounding is imparted to the edge of the substrate. As a result, some amount of edge roll-off is inevitably imparted to the substrate, generally beginning several millimeters from the edge.
Edge roll-off (ERO) is generally quantified by such metrics as ESFQR and ZDD, which are known in the industry. When using ESFQR (Edge flatness metric, Sector based, Front surface referenced, least sQuares fit reference plane, Range of the data within the sector), the flatness is measured within a sector of the wafer, i.e. a fan-shaped area formed on the outer periphery of the wafer. FIG. 1A illustrates a plurality of sectors 101 on a wafer 100. In one embodiment, 72 sectors at 5 degree intervals can be provided on the periphery of wafer 100. FIG. 1B illustrates a cross-sectional view of wafer 100 and an exemplary distance (in this case, 1 mm from the apex of the edge) for calculating ESFQR.
FIG. 1C illustrates an exemplary sector 101 in which a plurality of measurements 102 have been taken. In one embodiment, these measurements 102 include thickness information provided by a sensor and its associated electronics. The data from measurements 102 can be averaged so as to provide a thickness along a radius vector 103 of sector 101. Note that although shown as measurements taken at the edge of the wafer (see, sectors 101 of wafer 100 in FIG. 1A), measurements 102 can also be taken for the whole wafer or other parts thereof.
Typical processing of information from the sensor would yield a profile curve indicating a thickness profile (thickness vs. radius). Typically, such a profile would have a plurality of small surface unevenness with larger anomalies classified as bumps or voids (i.e. inverted bumps). Generally, the profile of thickness has a gradual roll-off or reduction in thickness as the edge of the wafer is reached.
When an anomaly such as a bump is present, the change in the slope (i.e. the 2nd derivative) of the curve will go from negative to positive, thereby indicating a bump start radius (BSR). Second derivative processing converts the curve to a ZDD profile. An exemplary ZDD profile 105 (also called a ZDD metric) is shown in FIG. 1D. SEMI (Semiconductor Equipment and Materials International) Standard M68-1109, “Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a Curvature Metric, ZDD” is used by those in the semiconductor industry and describes ZDD profiles in greater detail. Because of the 2nd derivative properties, the beginning of the BSR (or void) is easily identifiable as the zero crossing (point 106) in ZDD profile 105.
FIG. 2 illustrates a simplified inspection system 200 in which a wafer 201 is spun about its center on its axis 202. A wafer measurement tool 203 includes a sensor 203A configured to measure the distance to wafer 201. The output 204 of 203A can be processed by a data interpreter 205 and a post-processing tool 206 (e.g. a microprocessor) to develop the ESFQR and/or ZDD profile. Output information regarding one or more metrics, profiles, or other parameters can be provided to a user interface 207 via standard I/O devices. The tolerance limits for ESFQR and ZDD are generally specified by IC device makers.
Developing and subsequently maintaining acceptable ERO tolerances in production is of vital importance to substrate manufacturers. Indeed, some processes, such as chemical-mechanical polishing (CMP), may alter the ERO of a substrate. In addition to the implications for lithographic depth-of-focus, the uniformity of downstream CMP processes could be affected if inadequate measures are taken to monitor ERO variation. Therefore, a need arises for improved inspection techniques and systems for determining ERO as well as surface topography.